Blind uVia in pad and export to LineSim

Discussion created by milostnik on Jan 19, 2012
Latest reply on Jan 20, 2012 by weston_beal



I am simulating a design made in BoardStation and transferred to BoardSim. There are blind uVia in pad, that connect to a differential pair. When I export the diff pair to LineSim, I don't see any uVia, though I see a truehole via in the signal path.


Is there any special setting that are needed in Hyperlynx to handle blind vVia in pad?


Here the details:


The first picture shows the signal path. In it the differential pair starts from a BGA chip with uVia in pad and goes directly down to signal layer 3. Then the signal proceeds in the board to the series capacitor, where a blind uVia in pad transfers the signal back to the surface, where it goes to the capacitor.

After that it goes for a very short piece on top to meet a truehole via that transports the signal back into the board down to the connector.

See picture j2_signal_in_boardsim.


In the detailed picture j2_signal_in_boardsim_detail, I can see the blind uVia in the pad of the capacitor, since there is a black point in the pad, same for the truehole via.


When I export it to LineSim, the only via in the signal path is the truehole via. I do not see the blind uVai in the BGA pad (or just after the symbol) as either I do not see any via before the capacitor. I the picture j2_signal_in_linesim I just see the truehole via. The signals are exported on the correct signal layer, and Hyperlynx is connecting the inner layers directly to the components.


Has anyone an idea if this is the standard behavior of Hyperlynx and if this is the correct behavior?

Is there any special setting that must be used if you are dealing with via in pad or blind vias in BaordSim before exporting?



Thanks for any help.