3 Replies Latest reply on Jan 20, 2012 2:29 PM by weston_beal

    Blind uVia in pad and export to LineSim




      I am simulating a design made in BoardStation and transferred to BoardSim. There are blind uVia in pad, that connect to a differential pair. When I export the diff pair to LineSim, I don't see any uVia, though I see a truehole via in the signal path.


      Is there any special setting that are needed in Hyperlynx to handle blind vVia in pad?


      Here the details:


      The first picture shows the signal path. In it the differential pair starts from a BGA chip with uVia in pad and goes directly down to signal layer 3. Then the signal proceeds in the board to the series capacitor, where a blind uVia in pad transfers the signal back to the surface, where it goes to the capacitor.

      After that it goes for a very short piece on top to meet a truehole via that transports the signal back into the board down to the connector.

      See picture j2_signal_in_boardsim.


      In the detailed picture j2_signal_in_boardsim_detail, I can see the blind uVia in the pad of the capacitor, since there is a black point in the pad, same for the truehole via.


      When I export it to LineSim, the only via in the signal path is the truehole via. I do not see the blind uVai in the BGA pad (or just after the symbol) as either I do not see any via before the capacitor. I the picture j2_signal_in_linesim I just see the truehole via. The signals are exported on the correct signal layer, and Hyperlynx is connecting the inner layers directly to the components.


      Has anyone an idea if this is the standard behavior of Hyperlynx and if this is the correct behavior?

      Is there any special setting that must be used if you are dealing with via in pad or blind vias in BaordSim before exporting?



      Thanks for any help.

        • 1. Re: Blind uVia in pad and export to LineSim

          This is normal operation for now. It might improve in the future as driver edge rates get faster. HyperLynx has always counted on the pin, including through-hole or via-in-pad, being modeled in the IBIS model.


          Most likely, the effect of the via is negligible, because it is so small. You can test this by adding the vias into the LineSim schematic (edit the size and layer span), and comparing the simulation results with and without the microvias.

          • 2. Re: Blind uVia in pad and export to LineSim

            Hello Weston,


            That is fascinating.


            I was always under the impression that the ibis model is a description of the chip's signal behavior at the pin., better said the influence of the path from the silicon die to the pin through the package in conjunction with the driver of the signal.


            What you are saying is that we should have different ibis models for different pads? And if I read correctly also for different via types.


            In the world of ibis, you get from a vendor only one ibis model, and I never heard that this ibis model would be modeled for a pad, a via in pad, a pad with blind via or a pad next to a true hole via, etc....

            I am also baffled, because the chip producer does not know how many layers the board will have, what kind of via I will use, where the via is placed and so on, when the ibis model is generated.

            Or is there a "standard pad" on which a ibis model is measured, and what are the correction you have to make to the ibis if the designed pad is different than the "standard pad".


            Could you please clarify this a little bit.


            Many thanks


            • 3. Re: Blind uVia in pad and export to LineSim

              As I said, this was normal operation in the past. It has been clear to HyperLynx marketing for some time that the IBIS package model is not adequate for modern technology. I stated that this would change in the future. I just ran some experiments in HyperLynx 8.2 pre-release, and found that it does a much better job of modeling the via in pad. If you would like to send my your HYP file, I can test the export of a few nets to LineSim schematics to see how 8.2 will model your microvia under the pad. You can zip the file and email it to weston_beal@mentor.com.