I might be able to offer some ideas for this. "text opens" reported during connectivity extraction phase are warnings, I think because they are often caused simply by misplaced text, and if it is a true open circuit then sould be reported as an error (an LVS discrepancy) during LVS comparison phase.
During connectivity extraction phase where it is reported as a warning, the source netlist (schematic) hasn't been read in and so at that moment there isn't a way to know if it's a real error or not.
Does that help, is that the sort of discussion you had in mind?
thanks for the quick reply Chris..
I agree with you that at the extraction phase I am seeing warning and no source has been read at this point.
But What I want is -> I don`t want to read the source at all, and I need posiible errors of OPEN circuits.
-> In a similar way I am getting the short errors. ( by just CONNECT and TEXT ATTACH statements.)
Can you please let me know, is there a way to highlight possible opens also ?
I see what you mean... Calibre has the statement for LVS ISOLATE SHORTS YES and a special output file is created from that for use with DRC-RVE while the similar capability doesn't exist for opens.
For debugging open circuit warnings I think cross probing with LVS-RVE can be useful. The following statement (or very similar) will be needed in the rule file used for connectivity extraction:
MASK SVDB DIRECTORY svdb QUERY
Then, after connectivity extraction such as "calibre -spice" the "svdb" directory can be loaded into LVS-RVE tool for highlighting each side of the open. You will need to highlight two nets because Calibre won't consider the open as one net, but rather as two nets with different net id's. You will be able to use the "net name" for one part of the open but the other part of the open will just have a "net id - number". That information should be there as part of the extraction warning.
Let me know if you need more details.