2 Replies Latest reply on Mar 12, 2012 7:52 AM by yu.yanfeng

    Post Layout Decoupling Analysis for a DDR interface

    raj.nikumbh

      Hello Experts,

       

      I am doing  a post layout interface my 16 layer board. I have calculated my Zo as 12.12 mOhm with dynamic current of 1.65A@1.8V and maximum percentage ripple as 2%. I see that this impedance is crossed at around 40MHz.

       

      I have good amount of decoupling with variuos values like 0,01uF,0.1uF, 0.47uF, 100uF. I also have 1.8V and GND plane.

       

      I want to understand under the lumped analysis should we below the impedance of 12.12mOhms throughout the frequency of 200MHz. In quick analysis I see almost all the caps as marignal in terms of placement.

       

      As decaps will provide decoupling till 100MHz only and after that it is plane that needs to take care till 400MHz.

       

      Let me know if my understanding is correct or I am missing something.

       

      Regards

      Raj Nikimbh

        • 1. Re: Post Layout Decoupling Analysis for a DDR interface
          strangd

          It sounds like you are at the point where the charge in the capacitors should be supplying power to the DDR and you are limited by the inductances of the capacitor interconnects and the plane inductance.  At this point you should be trying to reduce the plane inductance as the plane charge is the prime contributor of power to the rise in the signals.  In high speed circuits the caps are there to re-charge the plane not drive the chips.

           

          Do a web search on Bruce Archambeault and read some of his papers bypassing and SI and PI.

           

          Try reducing the laminate thickness between the power and return (ground) plane and /or increasing their size.  The boards that I do usually are 1-3 ohms but they are not commercial designs.  Still I would believe that you should try to reduce the 12 ohms by half.

           

          Good luck

          Dwain

          • 2. Re: Post Layout Decoupling Analysis for a DDR interface
            yu.yanfeng

            For dynamic current of 1.65A@1.8V and maximum percentage ripple as 2%, The Ztarget should be less than 21.8 milliohm up to your switching frequency.

            For Decap's effectness,  you may check the model of decap to see what is it's  resonant frequency , which is dertimed by the capacitance and ESL. Below it's resonant frequency, Capacitor is still capacitive.  On the board, Cap's mouting inductance(also spatial inductance) further decreases it's resonant frequency, so normally you see decaps  works below 200-300Mhz . For higher frequency, power/ground pair capacitance and on-pacakge-capacitance takes effect, finally  on-die capacitance do.

             

            Yanfeng