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Post Layout Decoupling Analysis for a DDR interface

Question asked by raj.nikumbh on Mar 12, 2012
Latest reply on Mar 12, 2012 by yu.yanfeng

Hello Experts,


I am doing  a post layout interface my 16 layer board. I have calculated my Zo as 12.12 mOhm with dynamic current of 1.65A@1.8V and maximum percentage ripple as 2%. I see that this impedance is crossed at around 40MHz.


I have good amount of decoupling with variuos values like 0,01uF,0.1uF, 0.47uF, 100uF. I also have 1.8V and GND plane.


I want to understand under the lumped analysis should we below the impedance of 12.12mOhms throughout the frequency of 200MHz. In quick analysis I see almost all the caps as marignal in terms of placement.


As decaps will provide decoupling till 100MHz only and after that it is plane that needs to take care till 400MHz.


Let me know if my understanding is correct or I am missing something.



Raj Nikimbh