3 Replies Latest reply on Jun 1, 2012 9:26 AM by weston_beal

    DDR3 CKE Assumptions

    jose.fundora

      Expert,

       

      On my DDRx Batch results it shows that the CKE signal is failing.  Looking through my FPGA datasheet and memory datasheet it really doesn't describe much about the signal.  All I understand about the signal is that it is an initialization signal that goes high and stays high.  Without the signal going high, the DDR3 memory ignores everything (data, clks, etc) from the FPGA until that signal goes high.  My question is does the simulation think it's failing on the only transition it makes or is it trying to switch this signal from low to high and vice versa throughout the simulation?  What assumptions does the simulator make about the signal?  Let me know if you have any questions on my wording or if I need to go into more detail.  Thanks!!!

        • 1. Re: DDR3 CKE Assumptions
          cristian.filip

          What type of failure are you getting SI or timing? What specific parameter? Have you loaded the corresponding waveforms into oscilloscope?

          You might want to have a look at Mentor’s AppNote 10685 that explains the right debugging methodology.

          • 2. Re: DDR3 CKE Assumptions
            jose.fundora

            I am getting fails on the SI.  It fails on the Monotonic, DC Thresholds Multi Cross, and Vref Threshold Multi Cross.  I will take a look at the oscope signal, but last I checked it seemed to have no issues.  I will also take a look at the appnote.  I will let you know what I find. 

            • 3. Re: DDR3 CKE Assumptions
              weston_beal

              Notice that the CKE signal is, by default, assigned to the control signal group. Therefore, it is analyzed the same as the other control signals, with a PRBS stimulus and setup and hold margins calculated at every transition. This gives you a good variety of scenarios when the CKE signal might switch. If, on the other hand, you don't want to see that many transitions on the CKE signal, you can simply not assign it to a signal group. Then HyperLynx will ignore it. You can run interactive simulations if you like, and have full control of the stimulus and timing analysis.

               

              Weston