On my DDRx Batch results it shows that the CKE signal is failing. Looking through my FPGA datasheet and memory datasheet it really doesn't describe much about the signal. All I understand about the signal is that it is an initialization signal that goes high and stays high. Without the signal going high, the DDR3 memory ignores everything (data, clks, etc) from the FPGA until that signal goes high. My question is does the simulation think it's failing on the only transition it makes or is it trying to switch this signal from low to high and vice versa throughout the simulation? What assumptions does the simulator make about the signal? Let me know if you have any questions on my wording or if I need to go into more detail. Thanks!!!