6 Replies Latest reply on Jun 8, 2012 7:46 AM by pcorbin

    How to add plated holes as part of a footprint without adding pins?


      I am creating a new footprint for an RF component, and placement of grounding vias is critical. So I would like to include ground vias as part of the footprint for the component.

      I have one pin assigned to the "ground" area for this footprint. I have associated copper on the top and bottom to this pin, and I need to add vias stitching them together.

      Is there a way to add these vias to the footprint without adding extra pins?

      If these vias must be called pins, will there be any problems caused by the extra pins that will not be part of the schematic symbol (decal)? Will the vias be preserved, and will they show up correctly in the drill file and n/c drill tape?




        • 1. Re: How to add plated holes as part of a footprint without adding pins?

          IN the past with say thermal pads in an IC that need

          vias, I include the "vias" as pins in the decal.


          I also include them in the schematic symbol  as pins.


          I just have a pneumonic as "GND VIA" or some such thing. That way they are

          part of the netlist. To us, the extra "pins" in the logic side of things is not

          a big deal and better than no having everything electrically buttoned up.


          I suppose you could add an extra gate to the logic for the "via pins" and just not place it -

          but then you would not have netlist continuity.

          • 2. Re: How to add plated holes as part of a footprint without adding pins?

            Here is how I do it:




            You can also search for other discussions on this topic.

            • 3. Re: How to add plated holes as part of a footprint without adding pins?

              You can add pins without showing them on the schematic when you create the logic part. It will be assinged to unused pins on the part and you'll just have to assign them to the specific nets on your schematic. just assign the part to your footprint and when you save it and used it in a schematic, it will show the unused pins.


              I hope this makes sense

              • 4. Re: How to add plated holes as part of a footprint without adding pins?

                You need to add them as pins (unless*)


                You do not have to add them to the logic part.    They will appear as signal pins in the properties, assign them to GND.  Signal pins are a bit of a risk to miss connecting, but if you change the net color for GND, you'll notice it.  If they are covered by a shape associated to a pin in the PCB decal, unconnected pins will generate DRC errors.  I also wrote a script that lists unconnected signal pins in a schematic, it's part of my final check.  Pretty safe method.


                The unless* part: It depends on what you mean by "critical location".  If you trust your designers to know their part requirements, let them add them as stitching vias.  That allows some flexibility.


                My (non EE) take on schematic representation:


                (With all due respect to jduquette, what he says is certainly the safe way)


                It's not up to the Design Engineer to decide what a schematic looks llike.  Consider the life of a schematic.  The Design Engineer spends 4 months working with a schematic of a circuit with which he is intimately familiar.  He probably sees that circuit in his head all night.  The next 10 years of that schematic's life are spent being shared with manufacturing and test engineers, agency approval personnel, product managers, inspection teams, rework, the next engineer to revise it........  This is why schematics need to represent the electrical circuit in a commonly understood format.  I've had engineers ask for some indecipherable schematics, because it's how they wanted to see it.  A design enginner's job is to think about the design, not the lifecycle of the board.  That's the PCB designer's job.  A different thought process.


                SO, in the case of multiple GND vias on a single pad.  Schematics are electrical, not mechanical representations of the functional circuit.  Unless there is some critical reason why these  pins function independently on a circuit (i.e., VDD, VSS, dedicated pins on the part, routing w/re to bypass caps), a single pin on the schematic represents the electrical function of that group of pins.  If the function is purely thermal, they don't belong on the schematic.  Think of the poor test engineer, looking at a 24 pin part on the board that has 32 pins on the schematic.


                A single PIN on a part should get a single PIN on a schematic.  If you had an impedance issue on a pin that required 8 GND vias when you route the board, would you show all those vias on the schematic?  Why is it different when you build those same vias into the part?


                It's Friday, good day to paint a target on myself/  No offense to EEs intentded, we just have to think differently!



                • 5. Re: How to add plated holes as part of a footprint without adding pins?

                  Good point about not wanting to confuse the test engineer.  Schematics rule! (usually...)  Different is good

                  • 6. Re: How to add plated holes as part of a footprint without adding pins?

                    You say potatoe I say potato....


                    If my pins are labelled "THERMAL VIA" or some other such designation, I don't believe

                    safety, Field ENG, marketing or any other interested spectator is going to have a fit.


                    Works for me and I have the security of knowing my netlist is tight and my "critical vias" or

                    whatever the case - are good to go.


                    To each his own, but I respectfully disgaree with your "Blanket Statement"


                    Sometimes depending on product, market specific needs or for other reasons a schematic may need to tell a different story

                    to different people. I know my schematics that are published for sometimes "consumer consumption" tell a much different story than

                    a schematic for a multiprocessor video board in a MIL box.