In the Oscilloscope window, you need to change the Stimulus from Global to Per Net/Pin.
Three more questions -
Can I enter timing information in prelayout DDR3 simulation?
When I tried to open the multiboard project in DDR3_postlayout.zip, I got - "Error loading hyp file" Screen shot attached. I tried to select manually, but still could not open the files.
How to disable ODT in simulation?
Message was edited by: hithesh
See this technote about running DDR analysis pre-layout.
The problem loading the multiboard projects comes from the fact that the project file uses complete path names for the constituent boards. If you place the design in a different directory than where it was created, then the directory names are incorrect. You can either reconstruct the multiboard project (difficult to do without prior knowledge of the system), or open the project file in a text editor and change the path names to match your local configuration.
Weston, I am referring to the app note(10858) you mention in your post.
The example in the appnote shows measurement of setup/hold time in the waveform by using cursors.
Can't I enter Tackmin, max etc value in a timing file?
What about skew in this case. Do I look at the controller datasheet and just add skew in my calculation?
How do I turn-off ODT and use an external resistor.
LineSim does not use the timing model files. Those are specifically for the DDR wizard in BoardSim.
The skew between DQ and DQS driven from the controller is set up on page 5 of the appnote. "In this case, the DQ driver is assigned with PRBS of bit period .75 ns and bit order of 5. The DQS differential driver is assigned with oscillator of 1.5ns period delayed by 0.375ns (1/4 of period).
"Figure 4: Assign Stimulus and Specify Initial Delay"
ODT is usually controlled with multiple selections in a [Model Selector]. You can select one of these models in the Model Assignment window, click Select... and click Model Selector... Choose a model that does not include the ODT behavior.
Select a part and then goto setup-->stimulus.
I opened the prj file in notepad and tried to edit the path. Still got the same error.
So, I just moved the files to default (C:) path. It worked.
I am using the ddr3_ctl.v for timing.
Just want to double check if the ibis models selected are correct (see screen shot). What does address_1p5x mean?
For the DDR3_data, should I select model of clk or data?
Also, can I simulate just one net instead of doing batch simulation. I tried selecting just DQ0, but the connector did not have a model and that was the end of it.
Another timing question - In the DDR3 datasheet of MT41J128M8, which one should i consider - Base spec or Vref at 1V/ns for setup/hold times.
Message was edited by: hithesh
hypx.png 39.5 KB
I was able to simulate just one net. I just edited the multiboard project and added J12 to J1 and J19 to J1 connection. Both connect to J1 on DIMM?
In the R column for J19, I entered 15 ohms (inferred from prelayout schematic). Is this correct.
The DQS waveform looks real ugly. I am not sure it's correct.
HYPERLYNX-SCOPE.pdf 27.9 KB